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Features
* Smart Card Interface
- Compliance with ISO 7816, EMV2000, GIE-CB, GSM and WHQL Standards Card Clock Stop High or Low for Card Power-down Modes Support Synchronous Cards with C4 and C8 Contacts Card Detection and Automatic de-activation Sequence Programmable Activation Sequence - Direct Connection to the Smart Card Logic Level Shifters Short Circuit Current Limitation (see electrical characteristics) 8kV+ ESD Protection (MIL/STD 883 Class 3) - Programmable Voltage 5V 5% at 65 mA (Class A) 3V 0.2V at 65 mA (Class B) 1.8V 0.14V at 40 mA - Low Ripple Noise: < 200 mV Versatile Host Interface - ICAM (Conditional Access) Compatible - Two Wire Interface (TWI) Link Programmable Address Allow up to 8 Devices - Programmable Interrupt Output - Automatic Level Shifter (1.6V to VCC) Reset Output Includes - Power-On Reset (POR) - Power-Fail Detector (PFD) High-efficiency Step-up Converter: 80 to 98% Efficiency Extended Voltage Operation: 3V to 5.5V Low Power Consumption - 180 mA Maximum In-rush Current - 30 A Typical Power-down Current (without Smart Card) 4 to 48 MHz Clock Input, 7 MHz Min for Step-up Converter (for AT83C24) 18 to 48MHz Clock input (for AT83C24NDS) Industrial Temperature Range: -40 to +85C Packages: SO28 and QFN28
*
Smart Card Reader Interface with Power Management AT83C24B AT83C24NDS
* * * * * * * *
Description
The AT83C24 is a smart card reader interface IC for smart card reader/writer applications such as EFT/POS terminals and set top boxes. It enables the management of any type of smart card from any kind of host. Up to 8 AT83C24 can be connected in parallel using the programmable TWI address. Its high efficiency DC/DC converter, low quiescent current in standby mode makes it particularly suited to low power and portable applications. The reduced bill of material allows reducing significantly the system cost. A sophisticated protection system guarantees timely and controlled shutdown upon error conditions. The AT83C24NDS is a dedicated version approved by NDS for use with NDS VideoGuard conditional access software in set-top boxes. All AT83C24 datasheet is applicable to AT83C24NDS. The main differences between AT83C24 and AT83C24NDS are listed below: 1/ CLASS A card supplied with CVCC = 4.75 to 5.25V for AT83C24NDS, CLASS A card supplied with CVCC = 4.6 to 5.25V for AT83C24 2/ 18MHz minimum on input clock for AT83C24NDS 3/ Up to 10F for capacitor connected on CVCC pin for AT83C24, 3.3F mandatory for AT83C24NDS
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Acronyms
TWI: Two-wire Interface POR: Power On Reset PFD: Power Fail Detect ART: Automatic Reset Transition ATR: Answer To Reset MSB: Most Significant Bit LSB: Least Significant bit SCIB: Smart Card Interface Bus
Block Diagram
VCC VSS LI CVSS
DVCC EVCC RESET
Voltage supervisor POR/PFD
CVCC
DC/DC Converter
CVCCIN
PRES/ INT A2/CK, A1/RST, A0/3V, CMDVCC SCL SDA
TWI Controller
Main Control & Logic Unit
Timer 16 Bits
Clocks Controller
CLK
Analog Drivers
CPRES CRST CIO, CC4, CC8 CCLK
I/O, C4, C8
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Pin Description
Pinouts (Top View)
28-pin SOIC Pinout QFN28 pinout
PRES/INT
CLK
2 3 4 5 6 7 8 9 10 11 12 13 14
RESET CMDVCC VSS
27 26 25 24 23 22 21 20 19 18 17 16 15
PRES/INT C4 I/O EVCC A2/CK A1/RST A0 /3V SCL SDA
CMDVCC
VSS
28 27 26 25 24 23 22 1 21 20 2 3 4 5 6 7 8 QFN 28 TOP VIEW 19 18 17 16
C8
C8 DVCC
1
28
DVCC
CLK
RESET
I/O EVCC
A2 /CK A1 /RST A0 /3V SCL
VCC
CVSS LI CVCC CVCCin CRST CCLK
VCC
LI
CVSS
NC
CIO CC8 CPRES
CVCC CVCCin
SDA 15 NC 9 10 11 12 13 14
CRST
CCLK
CPRES
NC
CC4
C4 CC8
NC
CC4
Note:
1. NC = Not Connected 2. SOIC and QFN packages are available for AT83C24 and for AT83C24NDS
Signals
Table 1. Ports Description
Pad Name Pad Internal Power Supply ESD Limits Pad Type Description Microcontroller Interface Function: TWI bus slave address selection input. A2/CKA1/RSTA0/3V EVCC 3 kV I A2/CK and A1/RST pins are respectively connected to CCLK and CRST signals in "transparent mode" (see page 17 ). A0/3V is used for hardware activation to select CVCC voltage (3V or 5V). The slave address of the device is based on the value present on A2, A1, A0 on the rising edge of RESET pin (see Table 2). In fact, the address is taken internally at the 11th CLK rising edge. Microcontroller Interface Function: Depending on IT_SEL value (see CONFIG4 register), PRES/INT EVCC 3 kV O opendrain PRES/INT outputs card presence status or interruptions (page 9) An internal Pull-up (typ 330k,see Table 18)to EVCC can be activated in the pad if necessary using INT_PULLUP bit (CONFIG4 register). Remark: during power up and before registers configuration, the PRES/INT signal must be ignored. Microcontroller Interface Function: * * I/O RESET VCC 3 kV opendrain * * Power-on reset A low level on this pin keeps the AT83C24 under reset even if applied on power-on. It also resets the AT83C24 if applied when the AT83C24 is running (see Power monitoring ). Asserting RESET when the chip is in Shut-down mode returns the chip to normal operation. AT83C24 is driving the Reset pin Low on power-on-reset or if power fail on VCC or DVCC (see POWERMON bit in CONFIG4 register), this can be used to reset or interrupt other devices. After reset, AT83C24 needs to be reconfigured before starting a new card session.
CIO
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Table 1. Ports Description (Continued)
Pad Name Pad Internal Power Supply ESD Limits 3 kV Pad Type I/O opendrain I/O opendrain Description Microcontroller Interface Function TWI serial data
SDA
VCC
SCL
VCC
3 kV
Microcontroller Interface Function TWI serial clock Microcontroller Interface Function
I/O
EVCC
3 kV
Copy of CIO pin and high level reference for EVCC. I/O An external pull up to EVCC is needed on IO pin. I/O is the reference level for EVCC if EVCC is connected to a capacitor. This feature is unused if EVCC is connected to VCC.
C4
EVCC
3 kV
I/O
Microcontroller Interface Function
(pull-up) Copy of Card CC4. 3 kV I/O Microcontroller Interface Function
C8
EVCC
(pull-up) Copy of Card CC8. 3 kV I I/O Microcontroller Interface Function Master Clock Smart card interface function
CLK
EVCC
CIO
CVCC
8 kV+
(pull-up) Card I/O I/O Smart card interface function
CC4
CVCC
8 kV+
(pull-up) Card C4 I/O Smart card interface function
CC8
CVCC
8 kV+
(pull-up) Card C8 Smart card interface function
CPRES
VCC
8 kV+
Card presence (pull-up) An internal Pull-up to VCC can be activated in the pad if necessary using PULLUP bit (CONFIG1 register). O Smart card interface function Card clock Smart card interface function Card reset Microcontroller Interface Function: Activation/Shutdown of the smart card Interface. Supply Voltage VCC is used to power the internal voltage regulators and I/O buffers. DC/DC Input LI must be tied to VCC pin through an external coil (typically 4.7 H) and provides the current for the charge pump of the DC/DC converter. It may be directly connected to VCC if the step-up converter is not used (see STEPREG bit in CONFIG4 register and see minimum VCC values in Table 20 (class A) and Table 21 (class B)).
I
CCLK
CVCC
8 kV+
CRST
CVCC
8 kV+
O I (pull-up)
CMDVCC
EVCC
3 kV+
VCC
3 kV+
PWR
LI
3 kV+
PWR
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AT83C24
Table 1. Ports Description (Continued)
Pad Name Pad Internal Power Supply ESD Limits Pad Type Description Card Supply Voltage CVCC 8 kV+ PWR CVCC is the programmable voltage output for the Card interface. It must be connected to external decoupling capacitors (see page 34 and page 36). CVCCin 8 kV+ PWR Card Supply Voltage This pin must be connected to CVCC. Digital Supply Voltage DVCC 3 kV+ PWR Is internally generated and used to supply the digital core. This pin has to be connected to an external capacitor of 100 nF and should not be connected to other devices. Extra Supply Voltage (Microcontroller power supply) EVCC is used to supply the internal level shifters of host interface pins. EVCC 3 kV+ PWR EVCC voltage can be supplied from the external EVCC pin connected to the host power supply. If EVCC cannot be connected to the host power supply, it must be tied to an external capacitor. EVCC voltage can be generated internally by an automatic follow up of the logic high level on the I/O pin. In this configuration, connect a 100 nF + 100kOhms in parallel between EVCC pin and VSS pin. CVSS VSS 8 kV+ GND GND DC/DC Ground CVSS is used to sink high shunt currents from the external coil. Ground
Note:
ESD Test conditions: 3 positive and 3 negative pulses on each pin versus GND. Pulses generated according to Mil/STD 883 Class3. Recommended capacitors soldered on CVCC and VCC pins.
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Operational Modes
TWI Bus Control
The Atmel Two-wire Interface (TWI) interconnects components on a unique two-wire bus, made up of one clock line and one data line with speeds of up to 400 Kbits per second, based on a byte-oriented transfer format. The TWI-bus interface can be used: - - - - - - - - - - - - To configure the AT83C24 To select the operating mode of the card: 1.8V, 3V or 5V To configure the automatic activation sequence To start or stop sessions (activation and de-activation sequences) To initiate a warm reset To control the clock to the card in active mode To control the clock to the card in stand-by mode (stop LOW, stop HIGH or running) To enter or leave the card stand-by or power-down modes To select the interface (connection to the host I/O / C4/ C8) To request the status (card present or not, over-current and out of range supply voltage occurrence) To drive and monitor the card contacts by software To accurately measure the ATR delay when automatic activation is used
TWI Commands
Frame Structure
The structure of the TWI bus data frames is made of one or a series of write and read commands completed by STOP. Write commands to the AT83C24 have the structure: ADDRESS BYTE + COMMAND BYTE + DATA BYTE(S) Read commands to the AT83C24 have the structure: ADDRESS BYTE + DATA BYTE(S) The ADDRESS BYTE is sampled on A2/CK, A1/RST, A0/3V after each reset (hard/soft/general call) but A2/CK, A1/RST, A0/3V can be used for transparent mode after the reset. Figure 1. Data transfer on TWI bus acknowledgement from slave command and/or data
SDA
Adresse byte
SCL 1 2 3 4
5
6
7
8
9
start condition
stop condition
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Address Byte
The first byte to send to the device is the address byte. The device controls if the hardware address (A2/CK, A1/RST, A0/3V pins on reset) corresponds to the address given in the address byte (A2, A1, A0 bits). If the level is not stable on A2/CK pin (or A1/RST pin, or A0/3V pin) at reset, the user has to send the commands to the possible address taken by the device. If A2/CK to A0/3V are tied to the host microcontroller and their reset values are unknown, a general call on the TWI bus allows to reset all the AT83C24 devices and set their address after A2/CK to A0/3V are fixed. Figure 2. Address Byte
b7 0
b6 1
b5 0
b4 0
b3 A2
b2 A1
b1 A0
b0 R/W
Slave Address on 7 Bits 1 for READ Command 0 for WRITE Command
Up to 8 devices can be connected on the same TWI bus. Each device is configured with a different combination on A2/CK, A1/RST, A0/3V pins. The corresponding address byte values for read/write operations are listed below. Table 2. Address Byte Values
A2 (A2/CK pin) 0 0 0 0 1 1 1 1 A1 (A1/RST pin) 0 0 1 1 0 0 1 1 A0 (A0/3V pin) 0 1 0 1 0 1 0 1 Address Byte for Read Command 0x41 0x43 0x45 0x47 0x49 0x4B 0x4D 0x4F Address Byte for Write Command 0x40 0x42 0x44 0x46 0x48 0x4A 0x4C 0x4E
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Write Commands
The write commands are: 1. Reset: Initializes all the logic and the TWI interface as after a power-up or power-fail reset. If a smart card is active when RESET falls, a deactivation sequence is performed. This is a onebyte command. 2. Write Config: Configures the device according to the last six bits in the CONFIG0 register and to the following four bytes in CONFIG1, CONFIG2, CONFIG3 then CONFIG4 registers. This is a five bytes command. Figure 3. Command byte format for Write CONFIG0 command
b7 1 b6 0 b5 X b4 X b3 X b2 X b1 X b0 X
CONFIG0 on 6 Bits
3. Write Timer: Program the 16-bit automatic reset transition timer with the following two bytes. This is a three bytes command. 4. Write Interface: Program the interface. This is a one-byte command. The MSB of the command byte is fixed at 0. 5. General Call Reset: A general call followed by the value 06h has the same effect as a Reset command. Table 3. Write Commands Description
Address Byte (See Table 2) 1. Reset 0100 A2A1A00 0100 A2A1A00 0100 A2A1A00 0100 A2A1A00 0000 0000 Command Byte 1111 1111 (10 + CONFIG0 6 bits) 1111 1100 (0+INTERFACE 7 bits) 0000 0110 CONFIG1 TIMER1 CONFIG2 TIMER0 CONFIG3 CONFIG4 Data Byte 1 Data Byte 2 Data Byte 3 Data Byte 4
2. Write config 3. Write Timer
4. Write Interface 5. General Call Reset
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AT83C24
Read Command
After the slave address has been configured, the read command allows to read one or several bytes in the following order: * * STATUS, CONFIG0, CONFIG1, CONFIG2, CONFIG3, INTERFACE, TIMER1, TIMER0, CAPTURE1, CAPTURE0 FFh is completing the transfer if the microcontroller attempts to read beyond the last byte.
Flags are only reset after the corresponding byte read has been acknowledged by the master.
Note:
Table 4. Read Command Description
Byte Description Address byte Data byte 1 Data byte 2 Data byte 3 Data byte 4 Data byte 5 Data byte 6 Data byte 7 Data byte 8 Data byte 9 Data byte 10 Data byte 11 Data byte 12 Byte Value 0100 A2A1A01 STATUS CONFIG0 CONFIG1 CONFIG2 CONFIG3 CONFIG4 INTERFACE TIMER 1 (MSB) TIMER 0 (LSB) CAPTURE 1 (MSB) CAPTURE 0 (LSB) 0xFF
Interrupts
The PRES/INT behavior depends on IT_SEL bit value (see CONFIG4 register). * If IT_SEL= 0, the PRES/INT output is High by default (on chip pull up or open drain). PRES/INT is driven Low by any of the following event: - - - - - INSERT bit set in CONFIG0 register (card insertion/extraction or bit set by software ) VCARD_INT bit set in STATUS register (the DC/DC output voltage has settled) over-current detection on CVCC VCARDERR bit set in CONFIG0 register (out of range voltage on CVCC or bit set by software) ATRERR bit set in CONFIG0 register (no ATR before the card clock counter overflows or bit set by software).This control of ATR timing is only available if ART bit =1.
If IT_SEL=0, a read command of STATUS register and of CONFIG0 register will release PRES/INT pin to high level. Several AT83C24 devices can share the same interrupt and the microcontroller can identify the interrupt sources by polling the status of the AT83C24 devices using TWI commands. * If IT_SEL= 1 (mandatory for NDS applications and for software compatibility with existing devices) the PRES/INT output is High to indicate a card is present and none of the following event has occured:
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- -
over-current detection on CVCC VCARDERR bit set in CONFIG0 register (out of range voltage on CVCC or bit set by software)
Card Presence Detection
The card presence is provided by the CPRES pin. The polarity of card presence contact is selected with the CARDDET bit (see CONFIG1 register). A programmable filtering is controlled with the CDS[2-0] bits (see CONFIG1 register). An internal pull-up on the CPRES pin can be disconnected in order to reduce the consumption, an external pull-up must then be connected to VCC. The PULLUP bit (see CONFIG1 register) controls this feature. The card presence switch is usually connected to Vss (card present if CPRES=1). The CARDDET bit must be set. The internal pull up can be connected. If the card presence contact is connected to Vcc (card present if CPRES=0), the internal pull-up must be disconnected (see PULLUP bit) and an external pull-down must be connected to the CPRES pin. An interrupt can be generated if a card is inserted or extracted (see interrupts ). Figure 4. Card Presence Input
VCC
External Pull-up Card Contact Presence
VSS VCC
VCC (See Table 18)
Internal Pull-up
PULLUP Bit
CARDDET Bit
= 1 Closed = 0 Open
= 1 No Card if CPRES = 0 = 0 No Card if CPRES = 1 FILTERING
CPRES
EVCC
Card Contact Presence
= 1 Closed = 0 Open
INT_PULLUP Bit IT_SEL Bit
CDS[2-0]
CARDIN bit
PRES/INT
External Pull-down IT Controller
= 1 Card Inserted = 0 No Card
VSS
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AT83C24
CIO, CC4, CC8 Controller
The CIO, CC4, CC8 output pins are driven respectively by CARDIO, CARDC4, CARDC8 bits values or by I/O, C4, C8 signal pins. This selection depends of the IODIS bit value. If IODIS is reset, data are bidirectional between respectively I/O, C4, C8 pins and CIO, CC4, CC8 pins. Figure 5. CIO, CC4, CC8 Block Diagram CVCC I/O EVCC C4 EVCC C8 CARDC8 bit CARDC4 bit CARDIO bit 0 1 CVCC 0 1 0 1 IODIS bit CVCC CC8 CC4 CIO
IO and CIO pins are linked together through the on chip level shifters if IODIS bit=0 in INTERFACE register. This is done automatically during an hardware activation. Their iddle level are 1. With IO high, CIO is pulled up. The same behavior is applicable on C4/ CC4 and C8/ CC8 pins. The maximum frequency on those lines depends on CLK frequency (3 clock rising edges to transfer). With CLK=27MHz, the maximum frequency on this line is 1.5MHz. Due to the minimum transfer delay allowed for NDS applications, the CLK minimum frequency is 18MHz.
Clock Controller
The clock controller generates two clocks (as shown in Figure 6 and Figure 7): 1. a clock for the CCLK: Four different sources can be used: CLK pin, DCCLK signal, CARDCK bit or A2/CK pin (in transparent mode). 2. a clock for DC/DC converter.
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Figure 6. Clock Block Diagram with Software Activation (see page 14) CLK DCCLK DCK[2:0] DC/DC
A2/CK
CKS[2:0] CARDCK bit
0 1
CCLK
CKSTOP bit
Figure 7. Clock Block Diagram with Hardware Activation (see page 14) CLK DCCLK DCK[2:0] DC/DC
A2/CK
CKS[2:0] CARDCK bit
0 1
CCLK
CMDVCC A1/RST CRST_SEL bit Hardware activation CKSTOP bit
CRST Controller
The CRST output pin is driven by the A1/RST pin signal pin or by the CARDRST bit value. This selection depends of the CRST_SEL bit value (see CONFIG4 register). If the CRST pin signal is driven by the CARDRST bit value, two modes are available: * * If the ART bit is reset, CRST pin is driven by CARDRST bit. If the ART bit is set, CRST pin is controlled and follows the "Automatic Reset Transition" (page 15).
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AT83C24
Figure 8. CRST Block Diagram with soft activation 0 CARDRST bit tb delay see Fig 12 ART bit 1 0 1 CRST
CRST_SEL bit = 0
Figure 9. CRST Block Diagram with Hardware Activation (CMDVCC pin used)
0 CARDRST bit 1 0 1 CRST
ART bit A1/RST
CMDVCC CRST_SEL bit = 1
Hardware activation
CMDVCC deactivation
activation
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Activation Sequence
Hardware Activation (DC/DC started with CMDVCC) Initial conditions: CARDDET bit must be configured in accordance to the smart card connector polarity. IT_SEL bit, CRST_SEL bit (see CONFIG4 register) must be set and CARDRST bit (see INTERFACE register) must be cleared. A smart card must be detected to enable to start the DC/DC (CVCC= 3V or 5V). The hardware activation sequence is started by hardware with CMDVCC pin going high to low. It follows this automatic sequence: * * * CIO / CC4 / CC8 and IO / C4 / C8 are respectively linked together (IODIS bit is cleared). The DC/DC is started and CVCC is set according to the A0/3V pin: 5V (Class A) if A0/3V is High and 3V (Class B) is A0/3V is Low. CCLK signal is enabled (CKSTOP bit cleared) when CVCC has settled to the programmed voltage (see Electrical Characteristics) and the level on A1/RST is 0. The CCLK source can be DCCLK signal, CLK signal , A2/CK signals or CARDCK bit (see Figures 5). CRST signal is linked with A1/RST pin as soon as A1/RST pin level is 0. A rising edge on A1/RST pin set the CRST pin.
1. The card must be deactivated to change the voltage.
*
Note:
Figure 10. Activation sequence with CMDVCC
CMDVCC
A1/RST
CCLK
CVCC
CRST
CIO
Note:
For NDS applications, the host usually starts activation with A1/RST = 0.
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AT83C24
Software Activation (DC/DC Started With Writing in VCARD[1:0] bits) and ART bit = 1 Initial conditions: CARDRST bit = 0, CKSTOP bit =1, IODIS bit = 1. The following sequence can be applied: 1. Card Voltage is set by software to the required value (VCARD[1:0] bits in CONFIG0 register). This writing starts the DC/DC. 2. Wait the end of the DC/DC init with a polling on VCARDOK bit (STATUS register) or wait for PRES/INT to go Low if enabled (if IT_SEL bit = 0 in CONFIG4 register). When VCARDOK bit is set (by hardware), CARDIO bit should be set by software. 3. CKSTOP, IODIS are programmed by software. CKSTOP bit is reset to have the clock running. IODIS is reset to drive the I/O, C4, C8 pins and the CIO,CC4, CC8 pins according to each other. 4. CARDRST bit (see INTERFACE register) is set by software. Automatic Reset Transition description: A 16-bit counter starts when CARDRST bit is set. It counts card clock cycles. The CRST signal is set when the counter reaches the TIMER[1-0] value which corresponds to the "tb" time (Figure 11).The counter is reseted when the CRST pin is released and it is stopped at the first start bit of the Answer To Request (ATR) on CIO pin. The CIO pin is not checked during the first 200 clock cycles (ta on Figure 11). If the ATR arrives before the counter reaches Timer[1-0] value, the activation sequence fails, the CRST signal is not set and the Capture[1-0] register contains the value of the counter at the arrival of the ATR. If the ATR arrives after the rising edge on CRST pin and before the card clock counter overflows (65535 clock cycles), the activation sequence completes. The Capture[1-0] register contains the value of the counter at the arrival of the ATR (tc time on Figure 11). Figure 11. Software activation with ART bit = 1 CARDRST bit set
CVCC
4 3
1
CRST
CCLK
CIO
ta
2
tb
tc
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ISO 7816 constraints: ta = 200 card clock cycles 400 card clock cycles< = tb 400 card clock cycles< = tc < = 40000 card clock cycles
Note: Timer[1-0] reset value is 400.
Software Activation (DC/DC Started by Writing in VCARD[1:0] bits) and ART bit = 0 The activation sequence is controlled by software using TWI commands, depending on the cards to support. For ISO 7816 cards, the following sequence can be applied: 1. Card Voltage is set by software to the required value (VCARD[1:0] bits in CONFIG0 register). This writing starts the DC/DC. 2. Wait of the end of the DC/DC init with a polling on VCARDOK bit (STATUS register) or wait for PRES/INT to go Low if enabled (if IT_SEL bit = 0 in CONFIG4 register). When VCARDOK bit is set (by hardware), CARDIO bit should be set by software. 3. CKSTOP, IODIS are programmed by software. CKSTOP bit is reset to have the clock running. IODIS is reset to drive the I/O, C4, C8 pins and the CIO,CC4, CC8 pins according to each other. 4. CRST pin is controlled by software using CARDRST bit (see INTERFACE register). Figure 12. Software activation without automatic control (ART bit = 0)
CVCC
4
CRST
1
3
CCLK
CIO
ATR 2
Note: Note: It is assumed that initially VCARD[1:0], CARDCK, CARDIO and CARDRST bits are cleared, CKSTOP and IODIS are set (those bits are further explained in the registers description) The user should check the AT83C24 status and possibly resume the activation sequence if one TWI transfer is not acknowledged during the activation sequence.
Deactivation Sequence
The card automatic deactivation is triggered when one the following condition occurs: * ICARDERR bit is set by hardware
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* * * * * * VCARDERR bit is set by hardware (or by software) INSERT is set and CARDIN is cleared (card extraction) SHUTDOWN is set by software CMDVCC goes from Low to High Power fail on VCC (see POWERMON bit in CONFIG4 register) Reset pin going low
It is a self-timed sequence which cannot be interrupted when started (see Figure 13). Each step is separated by a delay based on Td equal to 8 periods of the DC/DC clock, typically 2 s: 1. T0: CARDRST is cleared, SHUTDOWN bit set. 2. T0 + 5 x Td:CARDCK is cleared, CKSTOP, CARDIO and IODIS are set. 3. T0 + 6 x Td: CARDIO is cleared. 4. T0 + 7 x Td: VCARD[1-0] = 00. Figure 13. Deactivation Sequence
CVCC
CRST
CCLK
CIO, CC4, CC8
t1
Notes:
t2
Td
1. Setting ICARDERR by software does not trigger a deactivation. VCARDERR can be used to deactivate the card by software. 2. t1=5 to 5.5*Td, and t2=0.5*Td to Td.
Transparent Mode
If the microcontroller outputs ISO 7816 signals, a transparent mode allows to connect RST/CLK and I/O/C4/C8 signals after an electrical level control. The AT83C24 level shifters adapt the card signals to the smart card voltage selection. The CRST and CCLK microcontroller signals can be respectively connected to the A1/RST and A2/CK pins. The CRST_SEL bit (in CONFIG4 register) selects standard or transparent configuration for the CRST pin. CKS in CONFIG2 allows to select standard or transparent configuration for the CCLK pin. So CCLK and CRST are independent. A2/CK to A0/3V inputs always give the TWI address at reset. The A0/3V pin can be used for TWI addressing and easily connect two AT83C24 devices on the same TWI bus.
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Figure 14. Transparent Mode Description
Microcontroller AT83C24
CCLK CRST CIO CC4 CC8
A2/CK A1/RST I/O C4 C8
CCLK CRST CIO CC4 CC8 SMART CARD
Power Modes
Two power-down modes are available to reduce the AT83C24 power consumption (see STUTDOWN bit in CONFIG1 register and LP bits in CONFIG3 register). To enter in the mode number 4 (see Table 5), the sequence is the following: - - First select the Low-power mode by setting the LP bit The activation of the SHUTDOWN bit can then be done.
The AT83C24 exits Power-down if a software/hardware reset is done or if SHUTDOWN bit is cleared. The AT83C24 is then active immediately. Either a hardware reset or a TWI command clearing the SHUTDOWN bit can cause an exit from Power-down. The internal registers retain their value during the shutdown mode. In Power-down mode, the device is sleeping and waiting for a wake up condition. To reduce power consumption, the User should stop the clock on the CLK input after setting the SHUTDOWN bit. The clock can be enabled again just before exiting SHUTDOWN (at least 10 s before a START bit on SDA). Table 5. Power Modes Description
Typical Mode Number Shutdown Bit LP Bit STEPREG VCARD[1:0] Supply Current Description
1
0
X
0
11 160 mA 30 mA
Step up mode: VCC = 3V, CVCC = 5V, Icard = 65mA Icard = 0 Regulator mode: VCC = 5.25V, CVCC = 5V, Icvcc = 65mA DC/DC off, CLK = 10MHz, VCC=3V to 5V The TWI interface of the AT83C24 is active but its analog blocs are switched off to reduce the consumption Pulsed mode of the internal 3V logic regulator
2 3 4
0 0 1
X X 0
1 X X
11 00 00
70 mA 3 mA 90 A
5
1
1
X
00
30 A
18
AT83C24
4234F-SCR-10/05
AT83C24
Power Monitoring
The AT83C24 needs only one power supply to run: VCC. If the microcontroller outputs signals with a different electrical level, the host positive supply is connected to EVCC. EVCC and VCC pins can be connected together if they have the same voltage. * If EVCC and VCC have different electrical levels: The EVCC pin and RESET pin should be connected with a resistor bridge. RESET pin high level must be higher than VIH (see Table 19). When EVCC drops, RESET pin level drops too. A deactivation sequence starts if a card was active. Then the AT83C24 resets if RESET pin stays low. * If EVCC and VCC have the same value, then they should be connected: The AT83C24 integrates an internal 3V regulator to feed its logic from the VCC supply. The bit powermon allows the user to select if the internal PFD monitors VCC or the internal regulated 3V. If the PFD monitors VCC (POWERMON bit=0), a deactivation is performed if VCC falls below VPFDP (see VPFDP value in the datasheet). Same deactivation is performed if the internal 3V falls below VPFDP and POWERMON bit = 1.
19
4234F-SCR-10/05
Registers
Table 6. CONFIG0 (Config Byte 0)
7 1 Bit Number 7-6 6 0 5 ATRERR 4 INSERT 3 2 1 VCARD1 0 VCARD0
ICARDERR VCARDERR
Bit Mnemonic Description 1-0 These bits cannot be programmed and are read as 1-0. Answer to Reset Interrupt
5
ATRERR
This bit is set when the card clock counter overflows (no falling edge on CIO is received before the overflow of the card clock counter). This bit is cleared by hardware when this register is read. It can be set by software for test purpose. The reset value is 0. Card Insertion Interrupt This bit is set when a card is inserted or extracted: a change in CARDIN value filtered according to CDS[2-0]. After power up, if the level on CPRES pin is 0, then INSERT bit is set.
4
INSERT
It can be set by software for test purpose. This bit is cleared by hardware when this register is read. It cannot be cleared by software. The reset value is 0. Card Over Current Interrupt This bit is set when an over current is detected on CVCC. It can be set by software for test purpose (no card deactivation is performed, no IT is performed). This bit is cleared by hardware when this register is read. It cannot be cleared by software. The reset value is 0. Card Out of Range Voltage Interrupt This bit is set when the output voltage goes out of the voltage range specified by VCARD field. It can be set by software for test purpose and deactivate the card. This bit is cleared by hardware when this register is read. It cannot be cleared by software. The reset value is 0. Card Voltage Selection VCARD[1:0] = 00: 0V VCARD[1:0] = 01: 1.8V (see STEPREG bit) VCARD[1:0] = 10: 3V VCARD[1:0] = 11: 5V
3
ICARDERR
2
VCARDERR
1-0
VCARD[1:0]
VCARD[1:0] writing to 1.8V, 3V, 5V starts the DC/DC if a card is detected. VCARD[1:0] writing to 0 stops the DC/DC. No card deactivation is performed when the voltage is changed between 1.8V, 3V or 5V. The microcontroller should deactivate the card before changing the voltage. The reset value is 00.
20
AT83C24
4234F-SCR-10/05
AT83C24
Table 7. CONFIG 1 (Config Byte 1)
7
X
6
ART
5
SHUTDOWN
4
CARDDET
3
PULLUP
2
CDS2
1
CDS1
0
CDS0
Bit Number 7
Bit Mnemonic Description X This bit should not be set. Automatic Reset Transition Set this bit to have the CRST pin changed according to activation sequence.
6
ART
Clear this bit to have the CRST pin immediately following the value programmed in CARDRST. The reset value is 0. Shutdown
5
SHUTDOWN
Set this bit to reduce the power consumption. An automatic de-activation sequence will be done. Clear this bit to enable VCARD[1:0] selection. The reset value is 0. Card Presence Detection Polarity Set this bit to indicate the card presence detector is closed when no card is inserted (CPRES is low).
4
CARDDET Clear this bit to indicate the card presence detector is open when no card is inserted (CPRES is high).Changing CARDDET will set INSERT bit (see CONFIG0) even if no card is inserted or extracted. The reset value is 0. Pull-up Enable Set this bit to enable the internal pull-up on the CPRES pin. This allows to minimize the number of external components.
3
PULLUP
Clear this bit to disable the internal pull-up and minimize the power consumption when the card detection contact is on. Then an external pull-up must be connected to VCC (typically a 1 M resistor). The reset value is 1. Card Detection filtering CPRES is sampled by the master clock provided on CLK input. A change on CPRES is detected after: CDS[2-0] = 0: 0 sample(1) CDS[2-0] = 1: 4 identical samples CDS [2-0] = 2: 8 identical samples (reset value) CDS[2-0] = 3: 16 identical samples CDS[2-0] = 4: 32 identical samples CDS[2-0] = 5: 64 identical samples
2-0
CDS[2:0]
CDS[2-0] = 6: 128 identical samples CDS[2-0] = 7: 256 identical samples The reset value is 2.
Note:
When CDS[2-0] = 0 and IT_SEL = 0, PRES/INT = 1 when no card is present and PRES/INT = 0 when a card is inserted even if CLK is STOPPED. This can be used to wake up the external microcontroller and restart CLK when a card is inserted in the AT83C24.
If CDS[2-0] = 0, IT_SEL = 1 and CLK is stopped, a card insertion or extraction has no effect on PRES/INT pin.
21
4234F-SCR-10/05
Table 8. CONFIG2 (Config Byte 2)
7 X Bit Number 7 6 DCK2 5 DCK1 4 DCK0 3 X 2 CKS2 1 CKS1 0 CKS0
Bit Mnemonic Description X This bit should not be set. DC/DC Clock prescaler factor DCCLK is the DC/DC clock. It is the division of CLK input by DCK prescaler. DCK = 0: prescaler factor equals 1 (CLK = 4 to 4.61MHz) DCK [2:0] = 1: prescaler factor equals 2 (CLK = 7 to 9.25MHz) DCK [2:0] = 2: prescaler factor equals 4 (CLK = 14 to 18.5 MHz) DCK [2:0] = 3: prescaler factor equals 6 (CLK = 21 to 27.6 MHz) DCK [2:0] = 4: prescaler factor equals 8 (CLK = 28 to 34.8 MHz)
6-4
DCK[2:0]
DCK [2:0] = 5: prescaler factor equals 10 (CLK = 35 to 43 MHz) DCK [2:0] = 6: prescaler factor equals 12 (CLK = 43.1 to 48 MHz) DCK [2:0] = 7: reserved The reset value is 1. DCCLK must be as close as possible to 4 MHz with a duty cycle of 50%. DCK must be programmed before starting the DC/DC. The other values of CLK are not allowed. DCK has to be properly configured before resetting the STEPREG bit.
3
X
This bit should not be set. Card Clock prescaler factor CKS [2:0] = 0: CCLK = CLK (then the maximum frequency on CLK is 24 MHz) CKS [2:0] = 1: CCLK = DCCLK (DC/DC clock) CKS [2:0] = 2: CCLK = DCCLK / 2 CKS [2:0] = 3: CCLK = DCCLK / 4 CKS [2:0] = 4: CCLK = A2 CKS [2:0] = 5: CCLK = A2 / 2 CKS [2:0] = 6: CCLK = CLK / 2 CKS [2:0] = 7: CCLK = CLK / 4 The reset value is 0.
2-0
CKS[2:0]
Notes:
1. When this register is changed, a special logic insures no glitch occurs on the CCLK pin and actual configuration changes can be delayed by half a period to two periods of CCLK. 2. CCLK must be stopped with CKSTOP bit before switching from CKS = (0, 1, 2, 3, 6, 7) to CKS = (4, 5) or vice versa. 3. When DCK = 0, only CKS=4 and CKS=5 are allowed. 4. The user can't directly select A2 or A2/2 after a reset or when switching from CKS = (0, 1, 2, 3, 6, 7) to CKS = (4, 5). To select A2, the user should select A2/2 first and after A2. To select A2/2, the user should select A2 first and after A2/2.
22
AT83C24
4234F-SCR-10/05
AT83C24
Table 9. CONFIG3 (Config Byte 3)
7 EAUTO Bit Number 6 VEXT1 5 VEXT0 4 ICCADJ 3 LP 2 X 1 X 0 X
Bit Mnemonic Description EVCC voltage configuration: EAUTO VEXT1 VEXT0 0 0 EAUTO 0 0 1 0 0 1 1 X 0 EVCC = 0 the regulator is switched off. 1EVCC = 2.3V 0 EVCC = 1.8V 1 EVCC = 2.7V X EVCC voltage is the level detected on I/O input pin.
7-5
VEXT1 VEXT0
if EVCC is supplied from the external EVCC pin, the user can switch off the internal EVCC regulator to decrease the consumption. If EVCC is switched off, and no external EVCC is supplied, the AT83C24 is inactive until a hardware reset is done. The reset value is 100. CICC overflow adjust This bit controls the DC/DC sensitivity to any overflow current . 4 ICCADJ Set this bit to decrease the DC/DC sensitivity (CICC_ovf is increased by about 20%, see Electrical Characteristics). The start of the DC/DC with a high current load is easier. Clear this bit to have a normal configuration. The reset value is 0. Low-power Mode Set this bit to enable low-power mode during shutdown mode (pulsed mode activated). Clear this bit to disable low-power mode during shutdown mode. 3 LP The activation reference is the following: * First select the Low-power mode by setting LP bit. * The activation of SHUTDOWN bit can then be done. This bit as no effect when SHUTDOWN bit is cleared. The reset value is 0. 2 1 0 X X X This bit should not be set. This bit should not be set. This bit should not be set.
23
4234F-SCR-10/05
Table 10. CONFIG4 (Config Byte 4)
7 X Bit Number 7-5 6 X Bit Mnemonic X-X-X 5 X Description These bits should not be set. Step Regulator mode Clear this bit to enable the automatic step-up converter (CVCC is stable even if VCC is not higher than CVCC). 4 STEPREG Set this bit to permanently disable the step-up converter (CVCC is stable only if VCC is sufficiently higher than CVCC). This bit must be set before activating the DC/DC converter if no external coil is present. The reset value is 0. This bit must always be set if no external coil is used Internal pull-up Set this bit to activate the internal pull-up (connected internally to EVCC) on PRES/INT pin. 3 INT_PULLUP Clear this bit to deactivate the internal pull-up. PRES/INT is an open drain output with a programmable internal pull up. The reset value is 0. Power monitor 2 POWERMON Set this bit to monitor any glitch on the Digital Supply Voltage (DVCC) of the AT83C24. Clear this bit to monitor any glitch on VCC. The reset value is 0. Interrupt Select Set this bit to disable INSERT and VCARD_INT interrupts. Then PRES/INT is pulled up when a card is present and no error is detected. Clear this bit to have all the interrupt sources enabled and active Low. IT_SEL must be set to enable a hardware activation with CMDVCC. The reset value is 0. Card Reset Selection Set this bit to have the CRST pin driven by hardware through the A1 pin (only with hardware activation). 0 CRST_SEL Clear this bit to have the CRST pin driven by software through the CARDRST bit. CRST_SEL must be set when CMDVCC is used (hardware activation). The reset value is 0. 4 STEPREG 3 INT_PULLUP 2 POWERMON 1 IT_SEL 0 CRST_SEL
1
IT_SEL
24
AT83C24
4234F-SCR-10/05
AT83C24
Table 11. INTERFACE (Interface Byte)
7 0 Bit Number 7 6 IODIS Bit Mnemonic 0 5 CKSTOP Description This bit should not be set. Card I/O isolation Set this bit to drive the CIO, CC4, CC8 pins according to CARDIO, CARDC4, CARDC8 respectively and to put I/O, C4, C8 in Hi-Z. This can be used to have the I/O, and C4 and C8 pins of the host communicating with another AT83C24 interface, while CIO, CC4 and CC8 are driven by software (or if the card is in standby or power-down modes). Clear this bit to drive the I/O/CIO, C4/CC4 and C8/CC8 pins according to each other. This can be used to activate asynchronous cards. The reset value is 1. CARD Clock Stop Set this bit to stop CCLK according to CARDCK. This can be used to set asynchronous cards in power-down mode (GSM) or to drive CCLK by software. Clear this bit to have CCLK running according to CKS. This can be used to activate asynchronous cards. 5 CKSTOP 4 CARDRST 3 CARDC8 2 CARDC4 1 CARDCK 0 CARDIO
6
IODIS
Note:
1. When this bit is changed a special logic ensures that no glitch occurs on the CCLK pin and actual configuration changes can be delayed by half a period to two periods of CCLK. 2. CKSTOP must be set before switching on the DC/DC with VCARD[1:0].
The reset value is 1. Card Reset 4 CARDRST Set this bit to enter a reset sequence according to ART bit value. Clear this bit to drive a low level on the CRST pin. The reset value is 0. Card C8 3 CARDC8 Set this bit to drive the CC8 pin High with the on-chip pull-up (according to IODIS bit value). The pin can then be an input (read in STATUS register). Clear this bit to drive a low level on the CC8 pin (according to IODIS bit value). The reset value is 0. Card C4 2 CARDC4 Set this bit to drive the CC4 pin High with the on-chip pull-up (according to IODIS bit value). The pin can then be an input (read in STATUS register). Clear this bit to drive a low level on the CC4 pin (according to IODIS bit value). The reset value is 0. Card Clock 1 CARDCK Set this bit to set a high level on the CCLK pin (according to CKSTOP bit value). Clear this bit to drive a low level on the CCLK pin. The reset value is 0. Card I/O 0 CARDIO Set this bit to drive the CIO pin High with the on-chip pull-up (according to IODIS bit value). The pin can then be an input (read in STATUS register). Clear this bit to drive a low level on the CIO pin (according to IODIS bit value). The reset value is 0.
25
4234F-SCR-10/05
Table 12. STATUS (Status Byte)
7
CC8
6
CC4
5
CARDIN
4
VCARDOK
3
X
2
VCARD_INT
1
CRST
0
CIO
Bit Number
Bit Mnemonic
Description Card CC8
7
CC8
This bit provides the actual level on the CC8 pin when read. The reset value is 0. Card CC4
6
CC4
This bit provides the actual level on the CC4 pin when read. The reset value is 0. Card Presence Status
5
CARDIN
This bit is set when a card is detected. It is cleared otherwise. Card Voltage Status
4
VCARD_OK
This bit is set by the DCDC when the output voltage remains within the voltage range specified by VCARD[1:0] bits. It is cleared otherwise. The reset value is 0.
3
X
This bit should not be set. Card voltage interrupt
2
VCARD_INT
This bit is set when VCARD_OK bit is set. This bit is cleared when read by the microcontroller. The reset value is 0. Card RST
1
CRST
This bit provides the actual level on the CRST pin when read. The reset value is 0. Card I/O
0
CIO
This bit provides the actual level on the CIO pin when read. The reset value is 0.
Table 13. TIMER 1 (Timer MSB)
7 Bit 15 Bit Number 7-0 6 Bit 14 5 Bit 13 4 Bit 12 3 Bit 11 2 Bit 10 1 Bit 9 0 Bit 8
Bit Mnemonic Description Bits 15 - 8 Timer MSB (bits 15 to 8)
Reset value = 0x00000001
26
AT83C24
4234F-SCR-10/05
AT83C24
Table 14. TIMER 0 (Timer LSB)
7 Bit 7 Bit Number 7-0 6 Bit 6 5 Bit 5 4 Bit 4 3 Bit 3 2 Bit 2 1 Bit 1 0 Bit 0
Bit Mnemonic Description bits 7 - 0 Timer LSB (bits 7to 0)
Reset value = 0x10010000 Table 15. CAPTURE 1 (Capture MSB)
7 bit 15 Bit Number 7-0 6 bit 14 5 bit 13 4 bit 12 3 bit 11 2 bit 10 1 bit 9 0 bit 8
Bit Mnemonic Description bits 15 - 8 See "software activation with ART = 1", page 15.
Reset value = 0x00000000 Table 16. CAPTURE 0 (Capture LSB)
7 bit 7 Bit Number 7-0 6 bit 6 5 bit 5 4 bit 4 3 bit 3 2 bit 2 1 bit 1 0 bit 0
Bit Mnemonic Description bits 7 - 0 See "software activation with ART = 1", page 15.
Reset value = 0x00000000
27
4234F-SCR-10/05
Electrical Characteristics
Absolute Maximum Ratings *
Ambient Temperature Under Bias: .....................-40C to 85C Storage Temperature: ................................... -65C to +150C Voltage on VCC: ........................................ VSS -0.5V to +6.0V Voltage on SCIB pins (***): ......... CVSS -0.5V to CVCC + 0.5V Voltage on host interface pins:.......VSS -0.5V to EVCC + 0.5V Voltage on other pins: ...................... VSS -0.5V to VCC + 0.5V Power Dissipation: .......................................................... 1.5W Thermal resistor of QFN package..(**)............................35C/W Thermal resistor of SO package.................................48C/W *NOTICE: Stresses at or above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions may affect device reliability. Power Dissipation value is based on the maximum allowable die temperature and the thermal resistance of the package.
(**) Exposed die attached pad must be soldered to ground Thermal resistor are measured on multilayer PCB with 0 m/s air flow. (***) including shortages between any groups of smart card pins.
AC/DC Parameters EVCC connected to host power supply: from 1.6V to 5.5V.
TA = -40C to +85C; VSS = 0V; VCC = 3V to 5.5V. CLASS A card supplied with CVCC = 4.75 to 5.25V for AT83C24NDS CLASS A card supplied with CVCC = 4.6 to 5.25V for AT83C24 CLASS B card supplied with CVCC = 2.8V to 3.2V CLASS C card supplied with CVCC = 1.68V to 1.92V Table 17. Core (VCC)
Symbol VPFDP VPFDM trise, tfall Parameter Power fail high level threshold Power fail low level threshold VDD rise and fall time Min 2.4 2.25 1 s Typ 2.5 2.35 Max 2.6 2.45 600s Unit V V Not tested. Test Conditions
Table 18. Host Interface (I/O, C4, C8, CLK, A2, A1, A0, CMDVCC, PRES/INT)
Symbol VIL Input Low-voltage Parameter Min -0.5 Typ Max 0.3 x EVCC 0.25 x EVCC Unit V Test Conditions EVCC from 2.7V to VCC EVCC from 1.6 to 2.7V EAUTO=0 VIH Input High Voltage 0.7 x EVCC EVCC + 0.5 V EAUTO=1 EVCC from 1.6V to VCC
28
AT83C24
4234F-SCR-10/05
AT83C24
Table 18. Host Interface (I/O, C4, C8, CLK, A2, A1, A0, CMDVCC, PRES/INT) (Continued)
Symbol VOL Parameter Output Low-voltage (I/O, C4, C8, PRES/INT) Output High Voltage (C4, C8, PRES/INT) VOH on I/O depends on external pull up value Extra Supply Current Min Typ Max 0.05 0.4 0.8 x EVCC EVCC +3 Unit V V V mA Test Conditions IOL = -100 A IOL = -1.2 mA EVCC from 1.6V to VCC IOH = 100 A CL = 100 nF Short to VSS RPRES/INT PRES/INT weak pull-up output current 300 330 360 INT_PULLUP = 0: Internal pull-up active. CL = 100 nF, EIcc = +3 mA Vpeak on I/O from 1.6V to VCC EVCC EVCC pin not connected to a power supply Vpeak - 10 mV Vpeak Vpeak + 25 mV V EAUTO = 1: min duration 1s, min frequency 0.1Hz, spikes <50ns are filtered. EVCC EVCC pin connected to a power supply Vpeak 200mV EAUTO = 1 If DCK[2:0] =0 (CLK=4MHz to 4.61MHz), a duty cycle of 50% is needed. no constrainst on duty cycle
VOH EICC
CLK
Clock signal for AT83C24
4
48
MHz
CLK
Clock signal for AT83C24NDS
18
48
MHz
Table 19. Host Interface (SCL, SDA, RESET)
Symbol VIL Input Low-voltage Parameter Min -0.5 3 0.7 x VCC Typ Max 1.9 0.3 x VCC VCC + 0.5 0.4 0.1 x VCC Unit V Test Conditions VCC > 4.5V VCC <= 4.5V VCC > 4.5V VCC <= 4.5V IOL = -3 mA
VIH VOL VHIST
Input High Voltage Output Low-voltage Input trigger hysteresis
V V
Table 20. Smart Card Class A
Symbol Parameter Card Supply Current Capability Min 65 65 Card Supply Current Overflow: CICC_ovf ICCADJ = 0 (reset value) ICCADJ = 1 66 66 120 130 130 150 mA VCC from 3 to 5.5V Typ Max Unit Test Conditions VCC=3V to 5.5V, mA
STEPREG=0
CICC
VCC > 5.35V, STEPREG = 1
29
4234F-SCR-10/05
Table 20. Smart Card Class A
Symbol Parameter Min Typ Max Unit Test Conditions 0 < Icard < 60mA CL =10F Ripple on CVCC 60 150 200 350 mV for AT83C24 0 < Icard < 65mA CL = 3.3F for AT83C24NDS Max. charge 40 nA.s Spikes on CVCC 4.6 5.3 V Max. duration 400 ns Max. Icard variation 200 mA Vcardok up Vcardok down Vcardok high level threshold Vcardok low level threshold 4.8 4.6 4.75 4.9 4.8 4.8 V V AT83C24 AT83C24NDS Icard = 0, VCC > VPFDP TVHL CVCC valid to 0 180 500 250 750 s CL = 3.3 F Icard = 0 CL = 10 F Icard = 0 (see note 1) VCC = 3V, CL = 3.3F 180 TVLH CVCC 0 to Valid 110 240 170 250 250 300 250 s Icard = 65mA Icard = 0mA VCC = 3V, CL = 10F Icard = 65mA Icard = 0mA
Notes:
1. Capacitor: X7R type or X5R type, max ESR value is 30m (100kHz-100MHz), Replacing 3.3F by 2.2F in parrallel with 1F is better for ESR and noise reduction.
Table 21. Smart Card Class B
Symbol CICC Parameter Card Supply Current Capability Card Supply Current Overflow: CICC_ovf ICCADJ = 0 (reset value) ICCADJ = 1 Ripple on CVCC 66 66 130 140 60 140 150 200 350 mV 0 < Icard < 65mA CL =10F 0 < Icard < 65mA CL = 3.3F Maxi. charge 40 nA.s Spikes on CVCC 2.76 3.24 V Max. duration 400 ns Max. variation Icard 200mA Vcardok up Vcardok high level threshold Vcardok down Vcardok low level threshold 2.8 2.76 3 2.9 V V Icard = 0, VCC > VPFDP TVHL CVCC valid to 0 130 400 250 500 s CL = 3.3 F Icard = 0 (see note 1) CL = 10 F Icard = 0 mA VCC from 3.0 to 5.5V Min 65 65 Typ Max Unit mA Test Conditions VCC=3V to 5.5V, STEPREG=0 VCC > 5.35V, STEPREG = 1
30
AT83C24
4234F-SCR-10/05
AT83C24
Table 21. Smart Card Class B
Symbol Parameter Min Typ Max Unit Test Conditions VCC = 3V, CL = 3.3F 140 110 TVLH CVCC 0 to Valid 130 100 250 250 250 250 s VCC = 3V, CL = 10F Icard = 60mA Icard = 0mA Icard = 65mA Icard = 0mA
Notes:
1. Capacitor: X7R type or X5R type, max ESR value is 30m (100kHz-100MHz), Replacing 3.3F by 2.2F in parrallel with 1F is better for ESR and noise reduction.
Table 22. Smart Card Class C
Symbol CICC Parameter Card Supply Current Capability Card Supply Current Overflow: CICC_ovf ICCADJ = 0 (reset value) ICCADJ = 1 Spikes on CVCC Vcardok up Vcardok high level threshold Vcardok down TVHL Vcardok low level threshold 1.68 1.75 1.7 1.8 1.75 1.92 V V V s Icard = 0, CL = 10 F(1) CVCC = 1.8V to 0.4V Icard = 40mA, CL = 10 F(1) Icard = 0, CL = 10 F(1) s Icard = 40mA, CL = 3.3 F(1) Icard = 0, CL = 3.3 F(1) CVCC = 0.4 to VCARDOK 45 mA Min 40 Typ Max Unit mA Test Conditions VCC = 3V
CVCC valid to 0
180 200 100
300 300 150 80 100
TVLH
CVCC 0 to valid
50 60
Notes:
1. Capacitor: X7R type or X5R type, max ESR value is 30m (100kHz-100MHz), Replacing 3.3F by 2.2F in parrallel with 1F is better for ESR and noise reduction.
Table 23. Smart Card Clock (CCLK pin)
Symbol VOL Parameter Output Low-voltage Min 0 CVCC - 0.45 VOH Output High Voltage 0.7CVCC IOS Short Circuit Current -30 CVCC 30 16 tR tF Rise and Fall time 22.5 50 ns mA Typ Max 0.4 CVCC V Unit V Test Conditions IOL = -200 A CLASS A&B&C IOH = +200 A CLASS A&B CLASS C Short to GND or CVCC CL = 30 pF CLASS A CL = 30 pF CLASS B CL = 30 pF CLASS C measurement between 10% and 90% of CVCC
31
4234F-SCR-10/05
Table 23. Smart Card Clock (CCLK pin) (Continued)
Symbol Parameter Min 0.2 Rise and Fall Slew rate 0.12 V/ns Typ Max Unit Test Conditions CLASS A CCLK from 0.5 to 4.2V CLASS B CCLK from 0.5 to 0.85 x CVCC Low level voltage stability (taking into account PCB design) High level voltage stability (taking into account PCB design) -0.25 4.2 2.35 CVCC-0.4 CCLK Smart card clock frequency 0.5 CVCC+0.25 CVCC+0.25 CVCC+0.25 24 MHz V V CLASS A&B&C CVCC = CLASS A CVCC = CLASS B CLASS C CL = 30pF, CLK=48MHz
Table 24. Smart Card I/O (CIO, CC4, CC8 pins)
Symbol VIL IIL VIH IIH Parameter Input Low-voltage Input Low Current Input High Voltage Input High Current 0.6 x CVCC 0.7 x CVCC -20 Min -0.3V Typ Max 0.8 700 CVCC CVCC +20 0.45 VOL Output Low-voltage 0 0.3 0.3 0.75 x CVCC 0.9 x CVCC -15 -0.25 -0.25 -0.25 CVCC-0.5 CVCC CVCC +15 0.6 0.4 0.4 CVCC+0.25 V V V Unit V A V A IOL = -1 mA CLASS A IOL = -1 mA CLASS B IOL = -1 mA CLASS C IOH = 40 A CLASS A&B&C IOH = 0A, CLASS A&B mA Short to GND or CVCC CLASS A CLASS B CLASS C CVCC = CLASS A&B&C CL = 65 pF CLASS A: tR tF Output rise and fall time 0.1 measurement between 0.6V and 70% of CVCC CLASS B & C: measurement between 0.4V and 70% of CVCC tR tF Input rise and fall time 1 Test Conditions IIL = 500 A CVCC = CLASS A&B&C CVCC = CLASS A CVCC = CLASS B & C
VOH
Output High Voltage
V
IOS
Output Short Circuit Current Low level voltage stability (taking into account PCB design) High level voltage stability (taking into account PCB design)
s
s
CL = 65 pF
32
AT83C24
4234F-SCR-10/05
AT83C24
Table 25. Smart Card RST (CRST pin)
Symbol Parameter Min Typ Max 0.12 x CVCC VOL Output Low-voltage 0 0 0.4 0.2 V Unit Test Conditions IOL = -20 A CLASS A&B&C IOL = -200 A CLASS A IOL = -200 A CLASS B&C V mA IOH = 200 A CLASS A&B&C Short to GND or CVCC CL = 30pF tR tF Rise and Fall time 0.1 s measurement between 10% and 90% of CVCC CLASS A V CLASS B CLASS C CLASS A CVCC+0.25 V CLASS B CLASS C
VOH IOS
Output High Voltage Output High Current
0.9*CVCC -15
CVCC +15
Low level voltage stability (taking into account PCB design)
0.50V -0.25 0.30V 0.30V 4.2 2.35 CVCC-0.4
High level voltage stability (taking into account PCB design)
Table 26. Card Presence
Symbol Parameter Min Typ Max Unit Test Conditions Short to VSS RCPRES CPRES weak pull-up output current 300 330 360 PULLUP = 1: Internal pull-up active
Table 27. TWI (SDA, SCL pins)
Symbol tSU;DAT tHD;DAT tfDA Data set-up time Data hold time Fall time on SDA signal Parameter Min 20 10 Typ 10 0 50 Max Unit ns ns ns Test Conditions Not tested Not tested Not tested
33
4234F-SCR-10/05
Typical Application
Figure 1. Typical Standard Mode Application Diagram for 3 AT83C24 (up to 8 AT83C24 if needed)
EVCC
100nF
VCC
L1
4.7H
C13
C1
2.2F
EVCC
VCC
See note for I/O pull up SDA, SCL pullups Reset pullup
A1/RST A0/3V
TWI
SCL SDA RESET PRES/INT I/O, C4, C8 CLK
CRST CIO, CC4, CC8 CPRES CCLK CVCC, AT83C24 CVCCin
LI
VCC
A2/CK
CVSS
VSS
VCC
VCC
VSS
VSS
Card 1
100nF
2.2uF
1uF
RST
INT0 Px.y
C2
C3
C10
CVSS CVSS CVSS
DVCC
100nF
VSS
VCC
EVCC
100nF
L2
4.7H
EVCC
VCC
A1/RST A0/3V
XTAL1
XTAL2
VSS
CRST CIO, CC4, CC8 CPRES CCLK CVCC, CVCCin
LI
A2/CK
CVSS
VSS
Host MICROCONTROLLER
C14
C4
2.2F
VCC
VSS
VSS
Card 2
SCL SDA
4 to 48 MHz
AT83C24
100nF
2.2uF
1uF
RESET PRES/INT I/O, C4, C8 CLK EVCC
100nF
C5
C6
C11
CVSS CVSS CVSS VSS VSS
DVCC
100nF
VSS
VCC
L3
4.7H
C15
C5
2.2F
VCC
EVCC
A2/CK A1/RST A0/3V
VSS
VSS
VCC
CVSS
VSS
VSS
CRST CIO, CC4, CC8 CPRES CCLK
LI
Card 3
SCL SDA RESET PRES/INT I/O, C4, C8 CLK
AT83C24
CVCC, CVCCin
100nF
2.2uF
1uF
C8
C9
C12
DVCC
CVSS CVSS CVSS
100nF
VSS
Note:
1. The external resistor on I/O can be removed if the host pin has an internal resistor.
34
AT83C24
4234F-SCR-10/05
Typical NDS Application
Figure 2. Typical NDS Standard Mode Application Diagram for 1 AT83C24NDS.
EVCC
100nF
VCC
L1
4.7H
See note 2
C13
VSS
C1
2.2F
VSS
EVCC
VCC
LI
VCC
See note1 for I/O pull up SDA, SCL pullups Reset pullup
TWI
SCL SDA RESET PRES/INT I/O, C4, C8 CLK
RST
INT0 Px.y
CRST CIO, CC4, CC8 CCLK
VSS CVSS
VCC
Smart Card 1
CVCCin CVCC
1uF 2.2uF 100nF
Px.y Px.y Px.y
A2/CLK A1/RST A0/3V
C2
C3
C10
Host MICROCONTROLLER
XTAL1
XTAL2
CVSS CVSS CVSS
AT83C24NDS
DVCC
18.432 or 27MHz 100nF
CPRES card present
VSS
VSS VSS VSS
Note:
1. The external resistor on I/O can be removed if the host pin has an internal resistor. 2. The internal pull up on PRES/INT is disabled during reset (recommended external 20kOhms pull up). 3. Refer to application note for AT83C24NDS software configuration.
36
AT83C24
4234F-SCR-10/05
AT83C24
Ordering Information
Part Number AT83C24B-PRTIL(2) AT83C24B-PRRIL(2) AT83C24B-PRTIM(2) AT83C24B-PRRIM(2) AT83C24B-TISIL AT83C24B-TIRIL AT83C24B-TISIM AT83C24B-TIRIM Supply Voltage 3V to 5.5V 3V to 5.5V 4.00V to 5.5V 4.00V to 5.5V 3V to 5.5V 3V to 5.5V 4.00V to 5.5V 4.00V to 5.5V Temperature Range Industrial Industrial Industrial Industrial Industrial Industrial Industrial Industrial Package QFN28 QFN28 QFN28 QFN28 SO28 SO28 SO28 SO28 Packing Tray Tape&Reel Tray Tape&Reel Stick Tape&Reel Stick Tape&Reel
AT83C24NDS-PRTIL (1)(2) AT83C24NDS-PRRIL (1)(2) AT83C24NDS-PRTIM (1)(2) AT83C24NDS-PRRIM (1)(2) AT83C24NDS-TISIL (1) AT83C24NDS-TIRIL (1) AT83C24NDS-TISIM (1) AT83C24NDS-TIRIM (1)
3V to 5.5V 3V to 5.5V 4.00V to 5.5V 4.00V to 5.5V 3V to 5.5V 3V to 5.5V 4.00V to 5.5V 4.00V to 5.5V
Industrial Industrial Industrial Industrial Industrial Industrial Industrial Industrial
QFN28 QFN28 QFN28 QFN28 SO28 SO28 SO28 SO28
Tray Tape&Reel Tray Tape&Reel Stick Tape&Reel Stick Tape&Reel
AT83C24B-PRTUL(2) AT83C24B-PRRUL(2) AT83C24B-PRTUM(2) AT83C24B-PRRUM(2) AT83C24B-TISUL AT83C24B-TIRUL AT83C24B-TISUM AT83C24B-TIRUM
3V to 5.5V 3V to 5.5V 4.00V to 5.5V 4.00V to 5.5V 3V to 5.5V 3V to 5.5V 4.00V to 5.5V 4.00V to 5.5V
Industrial & Green Industrial & Green Industrial & Green Industrial & Green Industrial & Green Industrial & Green Industrial & Green Industrial & Green
QFN28 QFN28 QFN28 QFN28 SO28 SO28 SO28 SO28
Tray Tape&Reel Tray Tape&Reel Stick Tape&Reel Stick Tape&Reel
AT83C24NDS-PRTUL (1)(2) AT83C24NDS-PRRUL (1)(2) AT83C24NDS-PRTUM(1)(2) AT83C24NDS-PRRUM (1)(2)
3V to 5.5V 3V to 5.5V 4.00V to 5.5V 4.00V to 5.5V
Industrial & Green Industrial & Green Industrial & Green Industrial & Green
QFN28 QFN28 QFN28 QFN28
Tray Tape&Reel Tray Tape&Reel
37
4234F-SCR-10/05
Part Number AT83C24NDS-TISUL (1) AT83C24NDS-TIRUL (1) AT83C24NDS-TISUM (1) AT83C24NDS-TIRUM (1) Note: 2. Refer to index mark for proper placement.
Supply Voltage 3V to 5.5V 3V to 5.5V 4.00V to 5.5V 4.00V to 5.5V
Temperature Range Industrial & Green Industrial & Green Industrial & Green Industrial & Green
Package SO28 SO28 SO28 SO28
Packing Stick Tape&Reel Stick Tape&Reel
1. Enhanced AC/DC parameters, see first page for differences between AT83C24 and AT83C24NDS.
38
AT83C24
4234F-SCR-10/05
AT83C24
Package Drawings
QFN28
39
4234F-SCR-10/05
SO28
AT83C24
Datasheet Change Log
Changes from 4234A-05/03 to 4234B-02/04
1. Addition of CRST, CIO, CCLK controllers descriptions, page 10. 2. Update of Hardware\Software activation description, page 14. 3. Suppression of low voltage regulator mode for power down modes, page 18. 4. Modification of clock values in CONFIG2 regsiter, page 22. 5. Addition of a point on QFN pinout view, page2. 6. Update of electrical characteristics, page 28.
Changes from 4234B-02/04 to 4234C - 04/04 Changes from 4234C-04/04 to 4234D - 07/04
1. Addition of references in ordering information 2. Update of EVCC description 3. Update of CARDDET bit and INSERT bit description 1. Update for Rev 4 silicon version (index 4 on component). 2. Software workaround for A2 or A2/2 selection in CKS register. 3. Max speed on IO/CIO transfer 4. New conditions for hardware activation (see IT_SEL). 5. SO28 drawing package (error with SO32). 6. Adjusted electrical parameters for NDS compliance, pages 28, 29, 30.
Changes from 4234D-04/04 to 4234E - 09/04 Changes from 4234E - 09/04 to 4234F - 10/05
1. QFN28 new package drawing. 2. Clock input parameters for AT83C24 and AT83C24NDS.
1. Updated green product ordering information.
41
4234F-SCR-10/05
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4234F-SCR-10/05

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